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  • Produktbild: Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
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Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

19.11.2010

Verlag

Springer Netherland

Seitenzahl

186

Maße (L/B/H)

24/16/1,2 cm

Gewicht

336 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-90-481-7202-3

Beschreibung

Rezension

From the reviews:



"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool … . This book’s scope and range of pragmatic ideas make it valuable for a wide audience. … When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area … . It should resonate with students, researchers, and practical designers … ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

19.11.2010

Verlag

Springer Netherland

Seitenzahl

186

Maße (L/B/H)

24/16/1,2 cm

Gewicht

336 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-90-481-7202-3

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

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  • Produktbild: Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
  • Produktbild: Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
  • Foreword. Preface.

    1. INTRODUCTION. 1.1 Organization of the Book Chapters.

    2. EMBEDDED SOC APPLICATIONS. 2.1 Networking Domain. 2.2 Multimedia Domain. 2.3 Wireless Communications. 2.4 Application Trends. 2.5 First Order Application Partitioning.

    3. CLASSIFICATION OF PLATFORM ELEMENTS. 3.1 Architecture Metrics. 3.2 Processing Elements. 3.3 On-Chip Communication. 3.4 Summary.

    4. SYSTEM LEVEL DESIGN PRINCIPLES. 4.1 The Platform Based Design Paradigm. 4.2 Design Phases. 4.3 Abstraction Mechanisms. 4.4 Models of Computation. 4.5 Object versus Actor Oriented Design. 4.6 System Level Design Requirements.

    5. RELATED WORK. 5.1 Traditional HW/SW Co-Design. 5.2 SystemC based Transaction Level Modeling. 5.3 Current Research on MP-SoC Design Methodologies. 5.4 Summary.

    6. METHODOLOGY OVERVIEW. 6.1 Application Modeling. 6.2 Architecture Modeling. 6.3 Envisioned Design Flow. 6.4 MP-SoC Simulation Framework.

    7. UNIFIED TIMING MODEL. 7.1 Tagged Signal Model Introduction. 7.2 Reactive Process Network. 7.3 Architecture Model. 7.4 Performance Metrics. 7.5 Summary.

    8. MP-SOC SIMULATION FRAMEWORK. 8.1 The Generic Synchronization Protocol. 8.2 Generic VPU Model. 8.3 NoC Framework. 8.4 Tool Support. 8.5 Summary.

    9. CASE STUDY. 9.1 IPv4 Forwarding with QoS Support. 9.2 Intel IXP2400 Reference NPU. 9.3 Custom IPv4 Platform. 9.4 Simulation Results.

    10. SUMMARY.

    Appendices. A The OSCI TLM Standard. B The OCPIP TL3 Channel. C The Architects View Framework.

    List of Figures. List of Tables. References. Index.