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VLSI Physical Design: From Graph Partitioning to Timing Closure From Graph Partitioning to Timing Closure

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

15.10.2014

Verlag

Springer Netherland

Seitenzahl

310

Maße (L/B/H)

23,5/15,5/1,8 cm

Gewicht

493 g

Auflage

1. Auflage

Originaltitel

Lienig: Layoutsynthese elektronischer Schaltungen

Sprache

Englisch

ISBN

978-94-007-9020-9

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

15.10.2014

Verlag

Springer Netherland

Seitenzahl

310

Maße (L/B/H)

23,5/15,5/1,8 cm

Gewicht

493 g

Auflage

1. Auflage

Originaltitel

Lienig: Layoutsynthese elektronischer Schaltungen

Sprache

Englisch

ISBN

978-94-007-9020-9

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: GPSR Kontakt

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  • Produktbild: VLSI Physical Design: From Graph Partitioning to Timing Closure
  • Produktbild: VLSI Physical Design: From Graph Partitioning to Timing Closure

  • 1 Introduction. 1.1 Electronic Design Automation (EDA). 1.2 VLSI Design Flow. 1.3 VLSI Design Styles. 1.4 Layout Layers and Design Rules. 1.5 Physical Design Optimizations. 1.6 Algorithms and Complexity. 1.7 Graph Theory Terminology. 1.8 Common EDA Terminology.

    2 Netlist and System Partitioning. 2.1 Introduction. 2.2 Terminology. 2.3 Optimization Goals. 2.4 Partitioning Algorithms. 2.5 A Framework for Multilevel Partitioning. 2.6 System Partitioning onto Multiple FPGAs. Chapter 2 Exercises.

    3 Chip Planning. 3.1 Introduction to Floorplanning. 3.2 Optimization Goals in Floorplanning. 3.3 Terminology. 3.4 Floorplan Representations. 3.5 Floorplanning Algorithms. 3.6 Pin Assignment. 3.7 Power and Ground Routing. Chapter 3 Exercises.

    4 Global and Detailed Placement. 4.1 Introduction. 4.2 Optimization Objectives. 4.3 Global Placement. 4.4 Legalization and Detailed Placement. Chapter 4 Exercises.

    5 Global Routing. 5.1 Introduction. 5.2 Terminology and Definitions. 5.3 Optimization Goals. 5.4 Representations of Routing Regions. 5.5 The Global Routing Flow. 5.6 Single-Net Routing. 5.7 Full-Netlist Routing. 5.8 Modern Global Routing. Chapter 5 Exercises.

    6 Detailed Routing. 6.1 Terminology. 6.2 Horizontal and Vertical Constraint Graphs. 6.3 Channel Routing Algorithms. 6.4 Switchbox Routing. 6.5 Over-the-Cell Routing Algorithms. 6.6 Modern Challenges in Detailed Routing. Chapter 6 Exercises.

    7 Specialized Routing. 7.1 Introduction to Area Routing. 7.2 Net Ordering in Area Routing. 7.3 Non-Manhattan Routing. 7.4 Basic Concepts in Clock Networks. 7.5 Modern Clock Tree Synthesis. Chapter 7 Exercises.

    8 Timing Closure. 8.1 Introduction. 8.2 Timing Analysis and Performance Constraints. 8.3 Timing-Driven Placement. 8.4 Timing-Driven Routing. 8.5 Physical Synthesis. 8.6 Performance-Driven Design Flow. 8.7 Conclusions. Chapter 8 Exercises.

    A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.