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Produktbild: Interconnect-Centric Design for Advanced SOC and NOC

Interconnect-Centric Design for Advanced SOC and NOC

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Beschreibung

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design....

Beschreibung

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Rezension

From the reviews:

"…a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues—including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field… this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book."
(IEEE Design & Test of Computers Magazine)

"The book is a collection of edited chapters written by various experts on NoC and on chip communications design … . The editors have carefully chosen the topics in this volume … . Clearly, the book covers an impressive breadth of topics … . Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list … . a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Design and design educators should take a close look at this book." (Grant Martin, IEEE Design & Test of Computers, March-April, 2005)

 

 

Zitat

From the reviews: "...a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues-including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field... this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book." (IEEE Design & Test of Computers Magazine)
"The book is a collection of edited chapters written by various experts on NoC and on chip communications design ... . The editors have carefully chosen the topics in this volume ... . Clearly, the book covers an impressive breadth of topics ... . Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list ... . a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Design and design educators should take a close look at this book." (Grant Martin, IEEE Design & Test of Computers, March-April, 2005)

Produktdetails

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Produktdetails

Format

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Erscheinungsdatum

20.03.2006
Herausgeber
Verlag Springer Us
Seitenzahl

454 (Printausgabe)
Dateigröße

7841 KB
Sprache

Englisch
EAN

9781402078361
Barrierefreiheit
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  • Produktbild: Interconnect-Centric Design for Advanced SOC and NOC
  • Preface 1.Introduction
    Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, Axel Jantsch 2. System-on-Chip Challenges in the Deep-Submicron Era
    Jan M. Rabaey PART I: PHYSICAL AND ELECTRICAL ISSUES 3. Wires as Interconnects
    Li-Rong Zheng, Hannu Tenhunen 4. Global Interconnect Analysis Towards NoC
    Tero Nurmi, Jian Liu, Dinesh Pamunuwa, Tapani Ahonen, Li-Rong Zheng,
    Jouni Isoaho, Hannu Tenhunen 5. Design Methodologies for On-Chip Inductive Interconnect
    Magdy A. El-Moursy, Eby Friedman 6. Clock Generation and Distribution for High-Performance SoC Designs
    Stefan Rusu PART II: LOGICAL AND ARCHITECTURAL ISSUES 7. Error-Tolerant Interconnect Schemes
    Heiko Zimmer, Axel Jantsch 8. Power Reduction Coding for Buses
    Paul P. Sotiriadis 9. Overview of SoC Buses
    Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen 10. From Buses to Networks
    David Siguenza Tortosa, Jari Nurmi 11. Arbitration and Routing Schemes for On-Chip Packet Networks
    Heikki Kariniemi, Jari Nurmi PART III: DESIGN METHODOLOGY AND TOOLS 12. Methodology and Techniques for Noise Reduction in SoC Interconnects
    Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila, Jouni Isoaho 13. Formal Communication Modeling and Refinement
    Juha Plosila, Tiberiu Seceleanu, Kaisa Sere 14. High-Level Communication Models for On-Chip Multiprocessor System Simulation
    Jan Madsen, Shankar Mahadevan, Kashif Virk 15. Socket-based Design Using Decoupled Interconnects
    Drew Wingard PART IV: APPLICATION CASES 16. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV
    Kees Goossens, Om. Prajash Gangwal, Jens Röver, A.P. Niranjan 17. A Brunch for the Coffee Table - Case Study in NOC Platform Design
    Tapani Ahonen, Seppo Virtanen, Juha Kylliäinen, Dragos Truscan, Tuukka Kasanko,
    David Sigüenza Tortosa, Tapio Ristimäki, Jani Paakkulainen, Tero Nurmi,
    Ilkka Saastamoinen, Hannu Isännäinen, Johan Lilius, Jari Nurmi, Jouni Isoaho