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  • Produktbild: Essderc ’89
  • Produktbild: Essderc ’89

Essderc ’89 19th European Solid State Device Research Conference, Berlin

51,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

01.07.2012

Herausgeber

Anton Heuberger + weitere

Verlag

Springer Berlin

Seitenzahl

963

Maße (L/B/H)

23,5/15,5/5,3 cm

Gewicht

1496 g

Auflage

Softcover reprint of the original 1st ed. 1989

Sprache

Englisch

ISBN

978-3-642-52316-8

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

01.07.2012

Herausgeber

Verlag

Springer Berlin

Seitenzahl

963

Maße (L/B/H)

23,5/15,5/5,3 cm

Gewicht

1496 g

Auflage

Softcover reprint of the original 1st ed. 1989

Sprache

Englisch

ISBN

978-3-642-52316-8

Herstelleradresse

Springer-Verlag GmbH
Tiergartenstr. 17
69121 Heidelberg
DE

Email: GPSR Kontakt

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  • Produktbild: Essderc ’89
  • Produktbild: Essderc ’89
  • GaAs electronic devices.- Deep submicron dry etching.- Characterization of hot carrier trapping in the gate oxide of MOSFETs.- The use of boron doped polysilicon in PMOS devices.- Semiconductor device fabrication with high energy ion implantation.- A self-aligned gate definition process with sub-micron gaps.- Novel submicron processes for shallow p+-n junctions.- Enhanced process window for BPSG flow in a salicide process using an LPCVD nitride cap layer.- Silicon oxidation rate dependence on dopant pile-up.- Beryllium and manganese diffusion in Ga0.47In0.53As during MBE-growth.- Quality and applications of In(Ga)AIAs-layers.- On the high-frequency behaviour of ohmic contacts.- Assessment of semi-insulating InP:Fe layers for substrate applications.- Investigation on p-buried GaAs MESFETs.- An InGaAs/GaAs strained superlattice MSM photodiode for fast light detection at 1.3?m.- Scaling-down of submicrometer GaAs MESFETs.- The mobility model in MINIMOS.- MESFET analysis with MINIMOS.- Numerical analysis of breakdown in silicon diodes.- A new algorithm to accelerate convergence in the simulation of semiconductor devices.- Narrow-width effects in submicron MOS ICs.- Simulation of parasitic currents and other effects in narrow channel devices.- 3D simulation of parasitic effects in EPROM cells.- Requirements for device and process modelling of submicron devices.- Geometry dependent bird’s beak formation for submicron LOCOS isolation.- Combination of LOCOS and BOX isolation for submicron CMOS technology.- Impact of oxide thinning at the LOCOS edge of MOS capacitors on constant current stress.- A self-aligned isolation oxide process before gate formation for enhanced packing density of megabit DRAMs.- Field isolation using shallow trenches for submicron CMOStechnology.- High performance submicron SILO process for high density EPROM memories using rapid thermal nitridation of silicon.- High speed BICMOS technology with emitter-base self-aligned structure.- Ohmic contacts to n-type GaAs using GeMoW metallization for self aligned processing.- Reliable, high temperature stable Schottky contacts to GaAs based on LaB6 diffusion barriers.- GaAs/InAs heterostructures grown by atomic layer epitaxy.- High temperature LPCVD of dielectrics on III–V substrates for device application.- Short-time diffusion of zinc into InP and InGaAsP from spin-on films.- Schottky barrier enhanœment on InP using pseudomorphic GaInP MBE layers.- Control of the Si3N4 InGaAs interfaces by constant capacitance transients.- Simulation of ion implantation into multilayer structures.- Simulation of the lateral spread of implanted ions: experiments.- The modeling and simulation of reactive ion etching rate using statistical method.- Two-dimensional aspects of ion enhanced reactive etching of silicon with SF6.- A yield modelling system for NMOS and CMOS IC.- Calculation of bipolar transistor base resistance using finite element method.- Efficient integration of device and circuit simulation.- Dopant activation and defect annihilation of heavily doped arsenic implanted silicon layers.- Self-aligned CoSi2 in a submicron CMOS process.- Reduction of titanium silicide degradation during boro-phosphosilicate glass reflow.- Shallow junctions fabrication by using molibdenum silicide and rapid thermal annealing.- A study of ultra shallow junctions by diffusion from self-aligned silicides.- The outdiffusion of boron and arsenic from pre-formed cobalt disilicide layers.- Ion-beam mixed MoSi2 layers: formation and contact properties.- An investigation into the parasitic effects affecting the operation of HEMT-based ICs.- Automated measurement of the bias dependence of low frequency small-signal parameter dispersions in GaAs MESFETs.- High speed Ga0.47In0.53As MISFETs grown by metal organic vapor phase epitaxy.- A resonant tunneling high electron mobility transistor.- Implanted-collector InGaAsP/InP heterojunction bipolar transistor.- 0.25 ?m all level e-beam pseudomorphic AIGaAs/lnGaAs MODFET with ft over 65 GHz.- Phase noise in HBT oscillator (abstract).- The influence of point defect concentrations on the diffusion of gold in silicon.- Quantification of diffusion mechanisms of boron, phosphorus, arsenic and antimony in silicon.- A consistent pair-diffusion based steady-state model for phosphorus diffusion.- Numerical simulation of gas flow and temperature in a diffusion furnace.- The impact of metal contamination on the quality of thermal SiO2.- A novel approach to realistic worst-case simulations of CMOS circuits.- Self-consistent modelling of npn and pnp transistors.- Technological challenge of artificial neural networks.- Progress in optoelectronic ICs.- The effect of rapid thermal annealing on the quality of thin thermal oxides.- Charge trapping in dry and pyrogenic gate oxides.- IC process compatible preparation of silicon interfaces using the silicon-to-silicon direct bonding method.- Electrical properties of ultra thin multilayer dielectrics on polysilicon.- Gate oxide reliability in a sealed interface local oxidation scheme.- Interface properties and channel mobility of plasma nitrided devices.- Influence of cleaning on SiO2 growth.- Assessment of pulse-to-pulse timing jitter in periodically gain-switched semiconductor lasers.- Monolithic Pb1-xSnxSe on Si infrared sensor array for the 8–12 ?m range.- InP based integrated laser driver circuit.- High-sensitivity, polysilicon-emitter phototransistors.- Ga0.96Al0.04Sb implanted avalanche photo-diode; perspective for a 2.55 ?m SAM APD photo detector.- Crack formation and selective growth in MOVPE-GaAs on Si and its application to OEICs.- Integration of GaAs LEDs on Si by epi-lift-off.- Submicron CMOS circuit simulation model accurate from liquid nitrogen to room temperature.- A new methodology to build-up accurate empirical models for VLSI MOSFETs.- Compact modelling of the MOSFET drain conductance.- A new analytical model of CMOS latch-up.- Physical modelling of bipolar mode field effect transistor (BMFET) for circuit simulation.- An analytical model for the vertical insulated gate bipolar transistor.- Effect of velocity saturation on small signal behaviour of submicron MOSFETs: analytical modelling and 2-D simulations.- Chemical sensors.- Fabrication and characterisation of pnp polysilicon emitter bipolar transistors.- BICMOSG3 cell — a novel high-speed DRAM cell taking full advantage of BICMOS technology.- 1.2 ?m BICMOS technology for mixed analog-digital applications.- Study of a polycide (WSi2/polysilicon) emitter for a CMOS compatible self-aligned bipolar transistor.- Physical analysis of peripheral base currents in an advanced polysilicon self-aligned bipolar transistor structure.- Sidewall contact for npn/pnp transistors by selective oxidation (SELOX).- A 10 GHz high performance BICMOS technology for mixed CMOS/ECL ICs.- Capacitance-voltage investigation of rechargeable traps in isotype laser heterojunctions.- Optical properties of GaInAs/InP multi-quantum wells grown by low pressure MOVPE.- Technology and characterization of a photoconductive device on InP.- MOMBE growth of GaInAs/InP structures: Quantum wells and selective epitaxy.- Coupling induced enhancement of interface recombination in GaAs multiple quantum well structures.- Scanning photoluminescence assessment MOCVD InGaAs/InP lattice mismatched heterostructures during the fabrication of photodiode arrays.- Investigation of GaAs/AlGaAs quantum well lasers by micro Raman spectroscopy.- Optimizing the epilayer doping concentration with respect to bipolar transistor performance in a low-power UHF-process.- An 1 GHz all-implanted vertical pnp transistor.- High voltage IC with vertical current flow and junction isolation.- Characterisation and performance of short-channel polysilicon thin-film transistors.- Analysis of the specific ON-resistance in conventional VDMOS transistors.- CMOS-compatible high-voltage complementary LDMOS devices.- Analysis of the modifications induced by electron irradiation on the electrical characteristics of high power GTOs.- Influence of top oxide thickness on electrical properties of ONO stacked insulators.- Electrical and optical spectroscopic characterization of oxide traps induced by hot hole injection.- Well technologies for half-micron CMOS processes.- An investigation into the effects of RTA processing on low frequency noise and other characteristics of CMOS FETs.- Avoiding lateral diffusion of dopants in n+/p+ polycide gates.- Electrical properties and sputter-etched induced defects in Ti-W/Si Schottky diodes.- Si/Si0.8Ge0.2 heterojunction bipolar transistors with ion implanted device contacts.- Cryoelectronic application of a hybrid device concept based on semiconducting and superconducting components.- Si permeable based transistor realization using a MOS compatible technology.- Enhanced transconductance in deep submicron MOSFET.- A planar reach-through p+np+ device for the detection of surface acoustic waves.- A monolithic integrated balanced mixer circuit for 9 to 12 GHz.- High temperature superconducting ceramic RF SQUID (abstract).- A monolithic integrated active thin film head for magnetic recording — an example for a combination technology suitable for smart sensors.- The effect of the metal, interface and semiconductor parameters on the electrical behaviour of Schottky junctions.- A new silicon diaphragm pressure sensor and its stress analysis.- A distribution function of injected electrons in the planar doped barrier transistors.- Dependence on gate length of electrical properties of self-aligned AlGaAs/GaAs HEMTs studied by Monte Carlo technique.- Frequency dependent CV measurements of GaAs/AlGaAs heterostructures.- Nuclear reaction analysis of electronic materials — part II: instability analysis of a Si:H solar cell materials.- Miniaturized accelerometers based on silicon micromachining techniques.- Sub-0.1 ?m silicon MOSFETs.- A TiN/TiSi2 interconnect structure durable for high temperature processing.- Formation of reliable Al-Si/Si contacts by chemical oxidation of the contact area.- The influence of tungsten contact filling on junction quality and contact resistance.- AlSi/Ti/AlSi multisandwich systems on TiN/Ti for VLSI interconnect applications.- A three-micron pitch, three layer metallization and dielectric scheme with application to a one micron CMOS process.- Comparison between different intermetallic dielectric processes and consequences on field transistor behavior.- Selective tungsten metallization for 0.5 ?m MOS processes.- Self-heating and temperature measurement in sub-?m-MOSFETs.- Latch-up free CMOS using buried polysilicon diodes.- Anomalous punchthrough in ULSI buried-channel P-MOSFETs.- Charge transport near the Si/SiO2 interface in MOSFET devices.- Characterization of MOSFET gate oxides by injection of controlled quantities of electrons.- The influence of an externally induced lateral electric field on bipolar transistors.- Current crowding in nested and self-aligned micrometric contacts.- Transient behaviour of UV-induced interface states in Au/SiO2/n-Si tunnel structures.- Advanced simulation for reliability optimization of submicron LDD MOSFETs.- Annealing of hot carrier damaged double metal MOSFET.- Hot-hole and electron effects in dynamically stressed n-MOSFETs.- Characterization of the hot carrier related MOS parameters using negative feedback circuits in VLSI CMOS.- The dependence of channel hot-carrier degradation on temperature in the range 77 K to 300 K.- Gate oxide thickness dependence of hot carrier induced degradation on PMOSFETs.- Ultimate speed of bipolar devices: Will the gap between CMOS and Bipolar be maintained? (abstract).- CMOS-SOI technologies for high speed and radiation hard circuits.- Novel electrical characterization of edge effects in SIMOX transistors.- A physical model for the characterization of SOI MOSFETs in linear operation.- The origin of the anomalous off-current in SOI-transistors.- Two-dimensional simulation of SOI MOSFETs.- Characterization of different SOI MOS technologies at cryogenic temperatures.- Analysis of charge conservation in isolated silicon regions.- An advanced fabrication process for 3D-CMOS devices.- Predicted propagation delay of Si/Si1-xGex heterojunction bipolar circuits.- Study of the effective valence band offset of Si/SiGe heterojunctions with a doping interface dipole.- Analysis of the punchthrough effect in walled emitter bipolar transistors.- Modelling forward-biased tunneling.- Pedestal collector in advanced bipolar technology for improved speed power performance.- Dependence of the propagation delay of an ECL gate on the transistor and circuit parameters.- Bandgap narrowing due to heavy doping in Si1-xGex layers.- Thermally activated failure modes and mechanisms of high electron mobility transistors.- Computer simulation of transient charge collection from ionizing radiation in silicon junctions.- Model for simulation of soft error rate of megabit DRAMs.- Optimization of submicron n-channel devices for performance and reliability.- Performance and reliability of sub-micron PMOS devices formed by implantation into silicide.- Performance drift mechanisms of 1.3 ?m lasers during aging.- Reliability and resistance minimization studies of the laser diffused diode links in wafer-scale-integration.- Limitations and use of analytical techniques for ULSI.- Is there anything beyond the 64MDRAM?.- Characterization and simulation of SOI-CMOS devices for 3D-integration.- Stacked CMOS technology by local overgrowth (LOG).- Buried and surface n-channel MOS transistors in SOI.- Explanation for the negative differential resistance in SOI-MOSFETs.- Modelling of single and double gate thin film SOI MOSFETs.- Gate oxide breakdown in a SOI CMOS process using MESA isolation.- Analytical modelling of the kink effect in MOS transistors.- Electrical characterization of a submicron titanium silicide local interconnect technology.- Stacked capacitor in trench cell for 16M — DRAM.- 0.5 ?m CMOS devices and circuit characterization.- VIPMOS, a buried local injector for EPROMs.- Leakage current limitations of trench cell for 16M DRAMs.- A highly reliable gate/n- overlapped transistor for mega-bit DRAMs.- Characterization of shallow junction ion implantation profiles: correlation between a noncontact photodisplacement thermal wave technique and rutherford backscattering analysis.- Non destructive electrical characterization of semiconducting layers by a novel microwave method.- Interconnect heating by pulsed DC.- Split-conductance, -capacitance and -current measurements in MOSFETs.- Determination of the emitter lateral doping profile for self-aligned bipolar-transistors.- A novel approach for an electrical vernier to measure mask misalignment.- Nuclear reaction analysis of electronic materials — part I: metal oxide semiconductor structures.- Author Index.