Analog Layout Generation for Performance and Manufacturability
-
- Hardcover
- Taschenbuch ausgewählt
-
Sprache:Englisch
95,99 €
UVP
109,99 €
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
09.12.2010
Abbildungen
XV, 175 p.
Verlag
Springer UsSeitenzahl
175
Maße (L/B/H)
23,5/15,5/1,1 cm
Gewicht
306 g
Auflage
Softcover reprint of hardcover 1st ed. 1999
Sprache
Englisch
ISBN
978-1-4419-5083-3
Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required.
In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In
Analog Layout Generation for Performance and
Manufacturability
, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a completeand sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction.
Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In
Analog
Layout Generation for Performance and Manufacturability
, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications.
Analog Layout Generation for Performance and Manufacturability
will be of interest to analog engineers, researchers and students.
Noch keine Bewertungen vorhanden
Verfassen Sie die erste Bewertung zu diesem Artikel
Helfen Sie anderen Kundinnen und Kunden durch Ihre Meinung.
Kurze Frage zu unserer Seite
Vielen Dank für Ihr Feedback
Wir nutzen Ihr Feedback, um unsere Produktseiten zu verbessern. Bitte haben Sie Verständnis, dass wir Ihnen keine Rückmeldung geben können. Falls Sie Kontakt mit uns aufnehmen möchten, können Sie sich aber gerne an unseren Kund*innenservice wenden.
zum Kundenservice