Introduction to Reconfigurable Computing Architectures, Algorithms, and Applications
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- Taschenbuch
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Sprache:Englisch
96,99 €
UVP
109,99 €
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Beschreibung
Produktdetails
Einband
Gebundene Ausgabe
Erscheinungsdatum
15.10.2007
Abbildungen
XXV, 359 p.
Verlag
Springer NetherlandSeitenzahl
359
Maße (L/B/H)
24,1/16/2,7 cm
Gewicht
694 g
Sprache
Englisch
ISBN
978-1-4020-6088-5
Architecture of reconfigurable systems, which presents the technology and the architecture used in fined-grained and those used in coarse-grained reconfigurable devices.
Design and implementation: This section deals with the implementation on reconfigurable system. It briefly covers the steps needed to implement application on today's FPGAs. And focus on the logic synthesis for FPGA, in particular LUT technology mapping.
High-Level Synthesis for Reconfigurable Devices: The high-level synthesis for reconfigurable systems, also known as temporal partitioning is presented here. Several temporal partitioning techniques are presented and explained.
Temporal placement: This section considers stand alone reconfigurable systems. Its assume that a kind of operating systems for reconfigurable systems is in charge of managing the resources of a given system and allocate space on a device for the computation of incoming tasks., and therefore presents several temporal placement approaches for off-line as well as on-line placement.
On-line and Dynamic Interconnection: This chapter reviews andexplains the different approaches for allowing communication between modules dynamically placed at run-time on a given device.
Designing a reconfigurable application on Xilinx Virtex FPGA: In this section, the different design approaches of partial reconfigurable systems on the Xilinx FPGAs that are one of the few one on the market with this feature, is explained.
System on programmable chip: System on programmable chip is a hot topic in reconfigurable computing. This is mainly the integration of a system made upon some peripheral (UART, Ethernet, VGA, etc.), but also computational (Coding, filter, etc.) hardware modules on one programmable chip. The current usable solutions are presented: The book furthermore focusses on the development of adaptive multiprocessors on chip, i.e. systems consisting of a set of Processors and exchangeable hardware accelerators.
Applications: This part covers the use of reconfigurable system in computer architecture (rapid prototyping, reconfigurable supercomputer, reconfigurable massively parallel computers) and algorithm better adapted for reconfigurable systems (distributed arithmetic, network packet processing, etc...)
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