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  • Produktbild: VLSI: Systems on a Chip
  • Produktbild: VLSI: Systems on a Chip
Band 34 - 13%

VLSI: Systems on a Chip IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI ’99) December 1–4, 1999, Lisboa, Portugal

Aus der Reihe IFIP Advances in Information and Communication Technology
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189,99 € UVP 219,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.12.1999

Herausgeber

Luis Miguel Silveira + weitere

Verlag

Springer Us

Seitenzahl

678

Maße (L/B/H)

24,2/16,7/4,7 cm

Gewicht

1198 g

Auflage

2000 edition

Sprache

Englisch

ISBN

978-0-7923-7731-3

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.12.1999

Herausgeber

Verlag

Springer Us

Seitenzahl

678

Maße (L/B/H)

24,2/16,7/4,7 cm

Gewicht

1198 g

Auflage

2000 edition

Sprache

Englisch

ISBN

978-0-7923-7731-3

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: gpsr@libri.de

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  • Produktbild: VLSI: Systems on a Chip
  • Produktbild: VLSI: Systems on a Chip
  • Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application.- An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices.- A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process.- A Low Power CMOS Micromixer for GHz Wireless Applications.- High Current, Low Voltage Current Mirrors and Applications.- Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications.- A Fast Parametric Model for Contact-Substrate Coupling.- A Feature Associative Processor for Image Recognition Based on A–D merged Architecture.- Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications.- Implementation of a Wavelet Transform Architecture for Image Processing.- Scalable Run Time Reconfigurable Architecture.- Frontier: A Fast Placement System For FPGAs.- Dynamically Reconfigurable Implementation of Control Circuits.- An IEEE Compliant Floating Point MAF.- Design and Analysis of On-Chip CPU Pipelined Caches.- Synchronous to Asynchronous Conversion — A Case Study: the Blowfish Algorithm Implementation.- Clock Distribution Strategy for IP-based Development.- An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures.- Single Ended Pass-Transistor Logic — A Comparison with CMOS and CPL.- Multithreshold Voltage Technology for Low Power Bus Architecture.- Integrating Dynamic Power Management in the Design Flow.- Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI.- On Defect-Level Estimation and the Clustering Effect.- FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits.- Design Error Diagnosis in DigitalCircuits without Error Model.- Efficient RLC Macromodels for Digital IC Interconnect.- A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications.- A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements.- RF Interface Design Using Mixed-Mode Methodology.- History-Based Dynamic Minimization During BDD Construction.- Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.- Satisfiability-Based Functional Delay Fault Testing.- Verification of Abstracted Instruction Cache of TITAC2: A Case Study.- Speeding Up Look-up-Table Driven Logic Simulation.- Efficient Verification of Behavioral Models Using Sequential Sampling Technique.- Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.- A Virtual CMOS Library Approach for Fast Layout Synthesis.- RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.- Designing a Mask Programmable Matrix for Sequential Circuits.- Placement Benchmarks for 3-D VLSI.- Substrate Noise: Analysis, Models, and Optimization.- Architectural Transformations for Hierarchical Algorithmic Descriptions.- An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.- Object-Oriented Modeling and Co-Simulation of Embedded Systems.- Architectural Synthesis with Interconnection Cost Control.- CAE Environment for Electromechanical Microsystems.- Cost Consideration for Application Specific Microsystems Physical Design Stages — A New Approach for Microtechnological Process Design.- Moving MEMS into Mainstream Applications: The MEMSCAP Solution.- Trends in RF Simulation Algorithms.- Device Modeling and Measurement for RF Systems.- Reconfigurable Computing: Viable Applications and Trends.-Hardware Synthesis from Term Rewriting Systems.- A Synthesis Algorithm for Modular Design of Pipelined Circuits.- A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS.- SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?.- ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.