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Produktbild: Phase-Locking in High-Performance System

Phase-Locking in High-Performance System From Devices to Architectures

251,99 €

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

13.02.2003

Verlag

John Wiley & Sons Inc

Seitenzahl

736

Maße (L/B/H)

28/21/3,9 cm

Gewicht

1757 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-0-471-44727-6

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

13.02.2003

Verlag

John Wiley & Sons Inc

Seitenzahl

736

Maße (L/B/H)

28/21/3,9 cm

Gewicht

1757 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-0-471-44727-6

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: gpsr@libri.de

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  • Produktbild: Phase-Locking in High-Performance System
  • Preface.
    About the Author.

    Part I: Original Contributions.

    Devices and Circuits for Phase-Locked Systems.

    Delay-Locked Loops - An Overview.

    Delta-Sigma Fractional-N Phase-Locked Loops.

    Design Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems.

    Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.

    Part II: Devices.

    Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors.

    The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC s.

    Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC s.

    Stacked Inductors and Transformers in CMOS Technology.

    Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies.

    A Q-Factor Enhancement Technique for MMIC Inductors.

    On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC s.

    The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors.

    Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium/BiCMOS Technology.

    Substrate Noise Coupling Through Planar Spiral Inductor.

    Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process.

    On the Use of MOS Varactors in RF VCO s.

    Part III: Phase Noise and Jitter.

    Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks.

    A Study of Phase Noise in CMOS Oscillators.

    A General Theory of Phase Noise in Electrical Oscillators.

    Physical Processes of Phase Noise in Differential LC Oscillators.

    Phase Noise in LC Oscillators.

    The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs.

    Jitter in Ring Oscillators.

    Jitter and Phase Noise in Ring Oscillators.

    A Study of Oscillator Jitter Due to Supply and Substrate Noise.

    Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise.

    On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops.

    Part IV: Building Blocks.

    A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications.

    A Fully Integrated VCO at 2 GHz.

    Tail Current Noise Suppression in RF CMOS VCOs.

    Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS.

    Analysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator.

    A 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO.

    A Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling.

    An Integrated 10/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process.

    Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology.

    35-GHz Static and 48-GHz Dynamic Frequency Divider IC s Using 0.2-[mu]m AlGaAs/GaAs-HEMT s.

    Superharmonic Injection-Locked Frequency Dividers.

    A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology.

    A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-[mu]m CMOS.

    A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops.

    High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler.

    A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC).

    A Simple Precharged CMOS Phase Frequency Detector.

    Part V: Clock Generation by PLLs and DLLs.

    A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.

    A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation.

    Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.

    A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz.

    A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL.

    Active GHz Clock Network Using Distributed PLLs.

    A Low-Noise Fast-Lock Pha