Invited Papers.- High Level System Design and Analysis Using Abstract State Machines.- Enriching the Software Development Process by Formal Methods.- Regular Papers.- Formal Program Development in Geometric Modeling.- Design of Distributed Multimedia Applications (DAMD).- Structured Formal Verification of a Fragment of the IBM S/390 Clock Chip.- Automated Test Set Generation for Statecharts.- Rigorous Compiler Implementation Correctness: How to Prove the Real Thing Correct.- Translation Validation: From DC+ to C.- A Practical Hierarchical Design by Timed Simulation Relations for Real-Time Systems.- A Lightweight Approach to Formal Methods.- An Open Environment for the Integration of Heterogeneous Modelling Techniques and Tools.- Integrating Domain Specific Language Design in the Software Life Cycle.- Flexible and Reliable Process Model Properties: An Integrated Approach.- A Symbolic Model Checker for ACTL.- Critical Systems Validation and Verification with CSP and FDR.- UniForM Perspectives for Formal Methods.- The UniForM WorkBench A Higher Order Tool Integration Framework.- Application Papers.- Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.- Formal Methods in the Specification of the Emergency Closing System of the Eastern Scheldt Storm Surge Barrier.- The New Topicality of Using Formal Models of Security Policy within the Security Engineering Process.- Tool Papers.- Towards Comprehensive Tool Support for Abstract State Machines: The ASM Workbench Tool Environment and Architecture.- The IFAD VDM Tools.- KIV 3.0 for Provably Correct Systems.- PVS: An Experience Report.- Overview over the Project Quest.- VSE: Controlling the Complexity in Formal Software Developments.- The wHOLe System.- Z/EVES Version 1.5: An Overview.